From: Les Cline

Hi Len,

The first description is what's implemented in the hardware of PIIX4 thru
ICH4-M. What's actually going on (in PIIX4 at least, I'm not sure what's behind
the scenes in the Mobile ICH's but it's probably the same), is that BM_RLD is a
mask bit for BM_STS (for both of the BM_STS functions, one of which is to
create a Break Event when BM_STS gets set due to a Bus Master Request occuring,
and the other is the state of the Software-visible bit that the OS needs to
watch). When BM_RLD = 1, BM_STS operates normally; when BM_RLD = 0, BM_STS
behaviors are suppressed (Break Event and setting of BM_STS are deferred until
RM_RLD gets set).

The second description is mostly correct, except that it misses the nuance that
C3 Exit can be caused by *either* a Bus Master Request (BM_STS got set) *or* an
Interrupt Request (BM_STS didn't get set) ... in the hardware, BM_RLD is *not*
an indicator of what actually happened, it's just an indicator of what the OS
is *permitting* to happen. 

If this second description is kept in the ACPI Spec, it would be better phrased
as follows (deleted text marked with [], new text marked with {}):
"The last hardware feature used in the C3 power state is the BM_RLD bit.
This bit determines if the Cx power state [was] {is permitted to be} exited as
a result
of bus master requests. If set, then the Cx power state [was] {is permitted to
be} exited
upon a request from a bus master. If reset, the power state [was] {is}
not exited upon bus master requests. In the C3 state, bus master
requests need to transition the CPU back to the C0 state
(as the system is capable of maintaining cache coherency),
but such a transition is not needed for the C2 state.
OSPM can optionally set this bit when using a C3 power state,
and clear it when using a C1 or C2 power state."

It appears that Intel Mobile Chipsets have taken the "optionally set ... clear"
part seriously: so far as I can tell, there's never been a need to dynamically
change the state of BM_RLD while entering or exiting a C-State ... it's
sufficient to just set it once (to enable BM_STS behaviors) and then leave it
alone. 

Here's something interesting ... this second text is different (and correct) in
the original ACPI 1.0 spec (12/22/1996), which says:
"The last hardware feature used in the C3 power state is the BM_RLD bit. 
This bit determines if the Cx power state is exited based on bus master
requests. 
If set, then the Cx power state is exited upon a request from a bus master; 
if reset, the power state is not exited upon bus master requests. In the C3 
state, bus master requests need to transition the CPU back to the C0 state 
(as the system is capable of maintaining cache coherency), but such a
transition is not needed for the C2 state. The ACPI driver can optionally 
set this bit when using a C3 power state, and clear it when using a C1-C2 power
state."

This (correct) text also exists in ACPI 1.0b spec, the new (broken) text first
appears in the ACPI 2.0 spec ... a few "is" mysteriously turned to "was," and
changed the meaning of the text. :-(

-Les